In a flip chip packaged integrated circuit, or simply “flip chip” for short, a die (chip) containing the integrated circuit has its active side facing a package substrate. In the flip chip process, also formally called the Controlled Collapse Chip Connection (C4) evaporative bump process, conductive bumps are formed and soldered to pads on the active side. The solder bumped die is then placed face down onto matching bonding pads on a multilayer organic package substrate. The assembly is reflowed so that the conductive bumps are soldered to pads on the package substrate to provide electrical connection between the active side of the integrated circuit and the package substrate. This electrical connection forms part of the so-called level 1 interconnect. The conductive bumps also provide a load bearing link between the die and the package substrate. Usually, the conductive bumps comprise solder.
After the die is attached to the substrate, an epoxy resin (or underfill) is usually applied at the interface between the die and the package substrate to help compensate for the difference in the coefficient of thermal expansion (CTE) between the die and the package substrate, and to prevent moisture from getting to the die surface. The flip chip may also be capped with a liquid epoxy for further protection.
FIG. 1 illustrates in simplified form a process comprising three steps to attach and solder the conductive bumps on a flip chip die to the package substrate, where the steps are labeled in sequential order as “A”, “B”, and “C”. In step A, die 102 held by tool 104 is dipped into flux resin 106. Arrow 108 pictorially represents this dipping process, where conductive bumps 110 are dipped into flux resin 106 and then pulled out. In step B, the numeric label 112 denotes solder wetting conductive bumps 110. Arrow 114 pictorially represents die 102 being placed onto package substrate 116. In step C, wavy lines 118 pictorially represent heat being applied to cause reflow of the solder so that conductive bumps 110 are soldered to pads (not shown) on package substrate 116.
As integrated circuits become more complex with higher numbers of input and output pads with a corresponding increase in the number of conductive bumps, the pitch of the conductive bumps is expected to increase. However, some problems that may arise with a tighter pitch using a reflow and attach process such as that illustrated in FIG. 1 are, to name just a few: opens or shorts leading to lower yield, poor wettability of the solder on the conductive bumps, and electrical connections between conductive bumps and pads that may fail over time. Warping of the die and package substrate may increase the likelihood of these problems.
A low cost manufacturing process to attach a die to a package substrate resulting in good yield and reliability in a tight pitch, flip chip integrated package is of utility.